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Am7922
Subscriber Line Interface Circuit
The Am7922 Subscriber Line Interface Circuit implements the basic telephone line interface functions, and enables the design of low cost, high performance, POTS line interface cards.
Control states: Active, Reverse Polarity, Tip Open, Ringing, Standby, and Open Circuit Low standby power (35 mW) -19 V to -58 V battery operation On-hook transmission Two-wire impedance set by single external impedance Available in PLCC and SOIC Programmable constant-current feed
BLOCK DIAGRAM
TMG
A(TIP)
HPA Input Decoder and Control HPB Two-Wire Interface
B(RING)
Signal Transmission Off-Hook Detector Power-Feed Controller
DA DB VBAT BGND VCC

DISTINCTIVE CHARACTERISTICS
Programmable loop-detect threshold Ground-key detector Programmable ring-trip detect threshold No -5 V supply required Current Gain = 500 On-chip Thermal Management (TMG) feature Three on-chip relay drivers and relay snubbers, 1 ringing and 2 general purpose Tip Open state for ground-start lines

Relay Driver Relay Driver Ring Relay Driver
RYOUT2 RYOUT1 RINGOUT D1 D2 C1 C2 C3 E1 DET VTX RSN RD RDC CAS
Ring-Trip Detector
VBREF
AGND/DGND
Publication# 080252 Rev: A Amendment: /0 Issue Date: October 1999
ORDERING INFORMATION Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am7922 -1 J C
TEMPERATURE RANGE C = Commercial (0C to +70C)*
PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032) S = 28-pin Small Outline Integrated Circuit (SOW 028)
PERFORMANCE GRADE -1 52 dB Longitudinal Balance, Polarity Reversal -2 63 dB Longitudinal Balance, Polarity Reversal -3 52 dB Longitudinal Balance, No Polarity Reversal -4 63 dB Longitudinal Balance, No Polarity Reversal
DEVICE NUMBER/DESCRIPTION Am7922 Subscriber Line Interface Circuit
Valid Combinations -1 -2 Am7922 -3 -4 SC JC
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity's standard military grade products.
Note: * Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
2
Am7922 Data Sheet
CONNECTION DIAGRAMS Top View
28-Pin SOIC
BGND VCC RINGOUT RYOUT1 RYOUT2 TMG VBAT D2 D1 E1 DET C3 C2 C1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
B(RING) A(TIP) DB DA RD HPB HPA VTX VBREF RSN AGND/DGND RDC NC CAS
32-Pin PLCC
RYOUT1 RINGOUT B(RING)
BGND
A(TIP) 31
VCC
4 RYOUT2 NC TMG VBAT D2 D1 NC E1 DET 5 6 7 8 9 10 11 12 13 14
3
2
1
32
DB 30 29 28 27 26 25 24 23 22 21 DA RD HPB HPA NC VTX VBREF RSN AGND RDC
15
16 C1
17 18 CAS NC
19 20 NC
C3 Notes: 1. Pin 1 is marked for orientation. 2. NC = No Connect
C2
SLIC Products
3
PIN DESCRIPTIONS
Pin Name AGND/DGND A(TIP) BGND B(RING) C3-C1 CAS Type Gnd Output Gnd Output Input Capacitor Analog and digital ground. Output of A(TIP) power amplifier. Battery (power) ground. Output of B(RING) power amplifier. Decoder. SLIC control pins. C3 is MSB and C1 is LSB. Anti-saturation capacitor. Pin for capacitor to filter reference voltage when operating in anti-saturation region. Relay driver control. D1 and D2 control the relay drivers RYOUT1 and RYOUT2. Logic Low on D1 activates the RYOUT1 relay driver. Logic Low on D2 activates the RYOUT2 relay driver. Ring-trip negative. Negative input to ring-trip comparator. Ring-trip positive. Positive input to ring-trip comparator. Switchhook detector. A logic Low indicates that selected condition is detected. The detect condition is selected by the logic inputs (C3-C1). The output is open-collector with a built-in 15 k pull-up resistor. E1 = 1 selects the switchhook detector. E1 = 0 selects the ground-key detector. Note: In the Tip Open state, the ground-key detector is active irrespective of E1. High-pass filter capacitor. A(TIP) side of high-pass filter capacitor. High-pass filter capacitor. B(RING) side of high-pass filter capacitor. No connect. This pin is not internally connected. Detect resistor. Detector threshold set and filter pin. DC feed resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). Ring relay driver. Open-collector driver with emitter internally connected to BGND. Receive summing node. The metallic current (both AC and DC) between A(TIP) and B(RING) is equal to 500 times the current into this pin. The networks which program receive gain, two-wire impedance, and feed resistance all connect to this node. Relay/switch driver. Open-collector driver with emitter internally connected to BGND. Relay/switch driver. Open-collector driver with emitter internally connected to BGND. Thermal management. External resistor connects between this pin and VBAT to offload power from SLIC. Battery supply and connection to substrate. This is a Legerity reserved pin and must always be connected to the VBAT pin. +5 V power supply. Transmit audio. This output is a 0.50 gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. Description
D2-D1 DA DB DET
Input Input Input Output
E1 HPA HPB NC RD RDC RINGOUT RSN RYOUT1 RYOUT2 TMG VBAT VBREF VCC VTX
Input Capacitor Capacitor -- Resistor Resistor Output Input Output Output Thermal Battery -- Power Output
4
Am7922 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage temperature ......................... -55C to +150C VCC with respect to AGND/DGND ..... -0.4 V to +7.0 V VBAT with respect to AGND/DGND: Continuous..................................... +0.4 V to -70 V 10 ms ............................................. +0.4 V to -75 V BGND with respect to AGND/DGND........ +3 V to -3 V A(TIP) or B(RING) to BGND: Continuous ......................................... VBAT to +1 V 10 ms (f = 0.1 Hz) ............................. -70 V to +5 V 1 s (f = 0.1 Hz) ................................ -80 V to +8 V 250 ns (f = 0.1 Hz) .......................... -90 V to +12 V Current from A(TIP) or B(RING).....................150 mA RINGOUT/RYOUT1,2 current............................50 mA RINGOUT/RYOUT1,2 voltage .............. BGND to +7 V RINGOUT/RYOUT1,2 transient .......... BGND to +10 V DA and DB inputs Voltage on ring-trip inputs ..................... VBAT to 0 V Current into ring-trip inputs .........................10 mA C3-C1, D2-D1, and E1 Input voltage .........................-0.4 V to VCC + 0.4 V Maximum power dissipation, continuous, TA = 70C, No heat sink (See note) In 32-pin PLCC package................................1.7 W In 28-pin SOIC package ................................1.4 W Thermal Data:................................................................ JA In 32-pin PLCC package....................... 43C/W typ In 28-pin SOIC package ....................... 60C/W typ ESD immunity/pin (HBM) ..................................1500 V
Note: Thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165C. The device should never see this temperature and operation above 145C junction temperature may degrade device reliability. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient temperature .............................0C to +70C* VCC .....................................................4.75 V to 5.25 V VBAT ......................................................-19 V to -58 V AGND/DGND .......................................................... 0 V BGND with respect to AGND/DGND ....................... -100 mV to +100 mV Load resistance on VTX to ground .............. 20 k min
The operating ranges define those limits between which the functionality of the device is guaranteed. * Functionality of the device from 0C to +70C is guaranteed by production testing. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
SLIC Products
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ELECTRICAL CHARACTERISTICS
Description Transmission Performance 2-wire return loss Analog output (VTX) impedance Analog (VTX) output offset voltage Overload level, 2-wire Overload level THD, Total Harmonic Distortion THD, On hook Longitudinal to metallic L-T, L-4 Active state On hook, RLAC = 600 0 dBm +7 dBm 0 dBm, RLAC = 600 Normal Polarity 0C to +70C -40C to +85C 0C to +70C -40C to +85C Reverse Polarity -40C to +85C 0C to +70C -40C to +85C Normal Polarity 0C to +70C -40C to +85C 0C to +70C -40C to +85C Reverse Polarity -40C to +85C 0C to +70C -40C to +85C 200 Hz to 3.4 kHz Active state 0 to 100 Hz RL = 600 RL = 600 RL = 600 RL = 600 0 dBm, 1 kHz 0 dBm, 1 kHz On hook 300 to 3.4 kHz relative to 1 kHz +3 dBm to -55 dBm relative to 0 dBm 0 dBm to -37 dBm +3 dBm to 0 dBm 0 dBm, 1 kHz 0C to +70C -40C to +85C 0C to +70C -40C to +85C -0.20 -6.22 -0.35 -6.37 -0.15 -0.15 -0.15 -0.35 4 -6.02 -50 2.5 0.77 -64 -55 -50 -40 -36 200 Hz to 3.4 kHz 26 3 20 +50 dB mV Vpk Vrms dB 2a 2b 5 1, 4 4 Test Conditions (see Note 1) Min Typ Max Unit Note
Longitudinal Capability (See Test Circuit D) -2,-4 -2,-4 -1,-3 -1,-3 -2 -1 -1 -2,-4 -2,-4 -1,-3 -1,-3 -2 -1 -1 63 58 52 50 54 52 50 dB 58 53 52 50 53 52 50 40 17 27 25 7 -83 +10 +12 -80 -78 +0.20 -5.82 +0.35 -5.67 +0.15 +0.15 +0.15 +0.35 s 4, 7 dB mArms /pin 8 4 4 4 4 4
4 4 4 4
200 Hz to 1 kHz
Longitudinal to metallic L-T, L-4
1 kHz to 3.4 kHz
Longitudinal signal generation 4-L Longitudinal current per pin (A or B) Longitudinal impedance at A or B Idle Channel Noise C-message weighted noise Psophometric weighted noise
dBrnc 4 dBmp
Insertion Loss and Balance Return Signal (See Test Circuits A and B) Gain accuracy 4- to 2-wire Gain accuracy 2- to 4-wire, 4- to 4-wire Gain accuracy, 4- to 2-wire Gain accuracy over frequency Gain tracking Gain tracking On hook Group delay 0 -6.02
Gain accuracy, 2- to 4-wire, 4- to 4-wire On hook
4
6
Am7922 Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description Line Characteristics IL, Short Loops, Active state IL, Long Loops, Active state IL, Accuracy, Standby state RLDC = 600 RLDC = 1930 , BAT = -42.75 V, TA = 25C BAT - 3 V IL = -----------------------------R L + 400 RL = 0 Active, A and B to ground 38.3 RL = 0 B to GND RA to BAT = 7 k, RB to GND = 100 50 Hz to 3.4 kHz (VRIPPLE = 100 mVrms) 50 Hz to 3.4 kHz (VRIPPLE = 500 mVpp) CAS pin to VBAT 15 -7.5 30 28 85 30 -5 40 50 170 25 35 130 RL = 600 RL = 300 Disconnect state Standby state Active state Disconnect state Standby state Active state 100 kHz to 30 MHz, (See Figure F) IRSN = 0 mA 200 Hz to 3.4 kHz 2.0 2.5 0.8 -75 -400 IOUT = 0.3 mA, 15 k to VCC IOUT = -0.1 mA, 15 k to VCC 2.4 0.40 40 A V 0 10 20 860 700 1.7 2.2 5.0 0.25 0.55 2.2 255 70 100 210 1200 1000 4.0 4.0 7.0 1.0 1.5 4.0 1.0 mW dB 5 75 40.3 100 56 T A = 25C 26.4 18 0.7IL 18 30 19 IL 30 100 120 A mA V A mA V 4 1.3IL mA 33.6 Test Conditions (See Note 1) Min Typ Max Unit Note
Constant-current region IL, Loop current, Disconnect state ILLIM VAB, Open Circuit voltage IA, Leakage, Tip Open state IB, Current, Tip Open state VA, Active Power Supply Rejection Ratio VCC VBAT Effective internal resistance Power Dissipation On hook, Disconnect state On hook, Standby state On hook, Active state Off hook, Standby state Off hook, Active state Supply Currents ICC, On-hook VCC supply current IBAT, On-hook VBAT supply current RFI Rejection RFI rejection Receive Summing Node (RSN) RSN DC voltage RSN impedance Logic Inputs (C3-C1, D2-D1, and E1) VIH, Input High voltage (except C3) VIH, C3 VIL, Input Low voltage IIH, Input High current IIL, Input Low current Logic Output (DET) VOL, Output Low voltage VOH, Output High voltage
k
4
mA
mVrms V
4
4
V
SLIC Products
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ELECTRICAL CHARACTERISTICS (continued)
Description Ring-Trip Detector Input (DA, DB) Bias current Offset voltage Loop Detector On threshold Off threshold Hysteresis IGK, Ground-key detector threshold RD = 35.4 k RD = 35.4 k RD = 35.4 k RL from BX to GND Active, Standby, and Tip open IOL = 40 mA VOH = +5 V IZ = 100 A IZ = 30 mA 6 7.2 10 5 9.4 8.8 11.7 10.4 1.3 9 13 mA 14.0 12.0 mA Source resistance = 2 M -500 -50 -50 0 +50 nA mV 6 Test Conditions (See Note 1) Min Typ Max Unit Note
Relay Driver Output (RINGOUT, RYOUT1, RYOUT2) On voltage Off leakage Zener breakover Zener On voltage Note: * Performance Grade +0.3 +0.7 100 V A V
RELAY DRIVER SCHEMATICS
RINGOUT
RYOUT1, RYOUT2
BGND
BGND
8
Am7922 Data Sheet
Notes: 1. Unless otherwise noted, test conditions are BAT = -48 V, VCC = +5 V, RL = 600 , RDC1 = RDC2 = 10.4K, RTMG = 1600 , RD = 35.4 k, no fuse resistors, CHP = 0.22 F, CDC = 0.33 F, CCAS = 0.33 F, D1 = 1N400x, two-wire AC input impedance is a 600 resistance synthesized by the programming network shown below. VTX RT1 = 75 k
RT2 = 75 k
CT1 = 120 pF
RSN RRX = 150 k 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire, AC-load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 6. Tested with 0 source impedance. 2 M is specified for system design only. 7. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1. The network reduces the group delay to less than 2 s and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the QSLACTM or DSLACTM device. 8. Minimum current level guaranteed not to cause a false loop detect. VRX
Table 1.
State 0 1 2 3 4 5 6 7 C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1
SLIC Decoding
E1 = 1 E1 = 0 DET Output X X Ground Key Ground Key Ring Trip Ring Trip Ground Key Ground Key DET Output X X Loop detector Ground Key Ring trip Ring trip Loop detector Loop detector
Two-Wire Status Reserved Reserved Active Polarity Reversal Tip Open Open Circuit Ringing Active Standby
SLIC Products
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Table 2. Z T = 250 ( Z 2WIN - 2R F )
User-Programmable Components
ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region.
Z RX
ZL 500Z T = ------------ * --------------------------------------------------G 42L Z T + 250 ( Z L + 2R F )
625 R DC1 + R DC2 = --------------I LOOP R DC1 + R DC2 C DC = 1.5 ms * ---------------------------------R DC1 * R DC2 390 355 RD ON = --------- , RD OFF = --------- , C D = 0.5 ms ---------------IT IT RD C CAS
1 = -----------------------------5 3.4 * 10 f c
RD and CD form the network connected from RD to AGND/ DGND and IT is the threshold current between on hook and off hook. CCAS is the regulator filter capacitor and fc is the desired filter cut-off frequency.
V BAT - 3 V I STANDBY = --------------------------------400 + R L
ae V BAT - 6 V o R TMG c --------------------------------- - 70 / e o ILOOP ( V BAT - 6 V - ( I L * R L ) ) P RTMG = ------------------------------------------------------------------------ * R TMG ( R TMG + 70 ) 2 2
Standby loop current (resistive region).
Thermal Management Equations (Normal Active and Tip Open States) RTMG is connected from TMG to VBAT and saves power within the SLIC in Active and Polarity Reversal states only. Power dissipated in the TMG resistor, RTMG, during Active and Polarity Reversal states.
P SLIC = V BAT * I L - P RTMG - R L ( I L ) + 0.13 W
2
Power dissipated in the SLIC while in Active and Polarity Reversal states.
10
Am7922 Data Sheet
DC FEED CHARACTERISTICS
50 45 40 35 Vab (volts) 30 25 20
4
3 2
1
15 10 5 0 0
RDC = RDC1 + RDC2 = 54.34 k V 5 BAT = -4810
15 20 Loop Current (mA) 25 30 35 40
RDC = RDC1 + RDC2 = 10.4K BAT = 48 V
Notes: 1. Constant current region:
625V AB = I L R L' = ---------- R L' , where R L' = R L + 2R F R DC R DC V AB = 47 V - I L ---------50
a) V AB 34.5 V b) V AB < 34.5 V
2. Battery-independent anti-sat:
3. Battery tracking anti-sat (off hook):
R DC V AB = 0.67 V BAT + 10.5 - I L --------150 R DC V AB = V BAT - 1.7 - I L --------200 R DC V AB = 0.67 V BAT + 8.5 - I L --------150 R DC V AB = V BAT - 4.4 - I L --------200
4. Battery tracking anti-sat (on hook):
a) V AB 34.5 V b) V AB < 34.5 V
a. Load Line (Typical)
SLIC Products
11
DC FEED CHARACTERISTICS (continued)
A
a RL b I SLIC RSN RDC1
L
RDC2 B RDC Feed current programmed by RDC1 and RDC2
CDC
b. Feed Programming Figure 1. DC Feed Characteristics
12
Am7922 Data Sheet
TEST CIRCUITS
A(TIP) SLIC VAB AGND RT RRX B(RING) RSN VTX
RL 2 VL RL 2
IL2-4 = 20 log (VTX / VAB) A. Two- to Four-Wire Insertion Loss
A(TIP) SLIC VAB RL
VTX
AGND
RT RRX
B(RING) RSN IL4-2 = 20 log (VAB / VRX) BRS = 20 log (VTX / VRX) B. Four- to Two-Wire Insertion Loss and Balance Return Signal VRX
1 C
<< RL S1 C VL VL
A(TIP) RL 2 VAB RL 2 B(RING) SLIC
VTX
AGND
RT
S2 RSN
RRX
VRX S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) L-4 Long. Bal. = 20 log (VTX / VL) S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX)
C. Longitudinal Balance
SLIC Products
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TEST CIRCUITS (continued)
ZD A(TIP) VTX RT1 AGND ZIN B(RING) RSN RRX RT2 CT1
R VS R VM
SLIC
ZD: The desired impedance; e.g., the characteristic impedance of the line Return loss = -20 log (2 VM / VS) D. Two-Wire Return Loss Test Circuit
L1 200
C1 50 A RF1 200 CAX 33 nF
RF2 B 50 CBX 33 nF
HF GEN 50
L2
C2
VTX
1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz E. RFI Test Circuit
SLIC under test
14
Am7922 Data Sheet
TEST CIRCUITS (continued)
+5 V DA DB RD 2.2 nF A(TIP) CHP B(RING) 2.2 nF RDC RINGOUT RYOUT1 RYOUT2 AGND/ DGND E1 D2 BGND D1 C3 BAT D1 TMG RTMG CAS CCAS DIGITAL GROUND VBREF VBAT C2 C1 DET ANALOG GROUND BATTERY GROUND CDC A(TIP) HPA HPB B(RING) RSN RDC1 RDC2 RT RRX VRX VTX VCC
RD VTX
F. Am7922 Test Circuit
SLIC Products
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PHYSICAL DIMENSIONS
BSC is an ANSI standard for Basic Centering. Dimensions are measured in inches. PL032
.447 .453 .485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
SOW028
28 15
.324 .350
.453 .500
0 8
1 .050 BSC
14
.016 .050
DETAIL A .697 .728
0.86 0.90 .002 .014
.080 .100
.006 .0125
0.14 0.20
.014 .024
0.045 MIN.
DETAIL A
16-038-SO28-2_AC SOW28 DF87 9-3-97 lv
16
Am7922 Data Sheet
Notes:
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The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice.
(c) 1999 Legerity, Inc. All rights reserved.
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